library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
Port (
oled_ss : out std_logic;
oled_res : out std_logic;
oled_dc : out std_logic;
oled_sck : out std_logic;
oled_sdi : out std_logic;
clk : in std_logic;
sw1 : in std_logic);
end main;
architecture RTL of main is
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component c15anp4
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal read_strobe : std_logic;
signal write_strobe : std_logic;
signal port000 : std_logic_vector(7 downto 0);
begin
processor: kcpsm6
generic map ( hwbuild => X"00",
interrupt_vector => X"3FF",
scratch_pad_memory_size => 64)
port map(
address => address,
instruction => instruction,
port_id => port_id,
interrupt => '0',
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
sleep => '0',
reset => '0',
clk => clk);
program: c15anp4
generic map( C_FAMILY => "S6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 0)
port map( address => address,
instruction => instruction,
enable => '1',
clk => clk);
out_ratch : process(clk) is
begin
if clk'event and clk='1' then
if write_strobe='1' then
if port_id ="00000000" then
port000 <= out_port;
end if;
end if;
end if;
end process out_ratch;
in_ratch : process(clk) is
begin
if clk'event and clk='1' then
if read_strobe='1' then
if port_id ="00000000" then
in_port(0) <= not sw1;
end if;
end if;
end if;
end process in_ratch;
oled_ss <= port000(0);
oled_res <= port000(1);
oled_dc <= port000(2);
oled_sck <= port000(3);
oled_sdi <= port000(4);
end RTL;
回路はLX-9 MicroBlazeのPMODのピンに超適当に配線です。
NET "oled_ss" LOC = D18;
NET "oled_res" LOC = D17;
NET "oled_dc" LOC = G14;
NET "oled_sck" LOC = F14;
NET "oled_sdi" LOC = F15;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
Port (
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
clk : in std_logic;
sw1 : in std_logic);
end main;
architecture RTL of main is
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component led_toggle
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal read_strobe : std_logic;
signal write_strobe : std_logic;
signal port000 : std_logic_vector(7 downto 0);
begin
processor: kcpsm6
generic map ( hwbuild => X"00",
interrupt_vector => X"3FF",
scratch_pad_memory_size => 64)
port map(
address => address,
instruction => instruction,
port_id => port_id,
interrupt => '0',
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
sleep => '0',
reset => '0',
clk => clk);
program_rom: led_toggle
generic map( C_FAMILY => "S6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 0)
port map( address => address,
instruction => instruction,
enable => '1',
clk => clk);
out_ratch : process(clk) is
begin
if clk'event and clk='1' then
if write_strobe='1' then
if port_id ="00000000" then
port000 <= out_port;
end if;
end if;
end if;
end process out_ratch;
in_ratch : process(clk) is
begin
if clk'event and clk='1' then
if read_strobe='1' then
if port_id ="00000000" then
in_port(0) <= not sw1;
end if;
end if;
end if;
end process in_ratch;
led1 <= port000(0);
led2 <= port000(1);
led3 <= port000(2);
led4 <= port000(3);
end RTL;
